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M50FLW040A bảng dữ liệu(PDF) 51 Page - STMicroelectronics |
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M50FLW040A bảng dữ liệu(HTML) 51 Page - STMicroelectronics |
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51 / 64 page ![]() M50FLW040A, M50FLW040B Part numbering 51/64 11 Part numbering Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Table 33. Ordering information scheme Example: M50FLW040 A K 5 T P Device Type M50 = Flash Memory for PC BIOS Architecture FL = Firmware Hub/Low Pin Count Interface Operating Voltage W = VCC = 3.0 to 3.6V Device Function 040 = 4 Mbit (x8), Uniform Blocks and Sectors Array Matrix A = 2 x 16 x 4KByte top sectors + 1 x 16 x 4KByte bottom sectors B = 1 x 16 x 4KByte top sectors + 2 x 16 x 4KByte bottom sectors(1) 1. Devices with this architecture are Not Recommended for New Design. Package K = PLCC32 NB = TSOP32: 8 x 14mm(2) 2. Devices delivered in this package are Not Recommended for New Design. N = TSOP40: 10 x 20 mm(2) Device Grade 5 = Temperature range –20 to 85 °C. Device tested with standard test flow Option blank = Standard Packing T = Tape and Reel Packing Plating Technology P or G = ECOPACK® (RoHs compliant) |
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