M25P64-VMF6TP datasheet(29/49 Pages) STMICROELECTRONICS

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M25P64

Instructions

29/49

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register provided that the Write Enable

Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless

of the whether Write Protect (W/VPP) is driven High or Low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W/VPP):

●

If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register

provided that the Write Enable Latch (WEL) bit has previously been set by a Write

Enable (WREN) instruction.

●

If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register

even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not

accepted for execution). As a consequence, all the data bytes in the memory area that

are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status

Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be

entered:

●

by setting the Status Register Write Disable (SRWD) bit after driving Write Protect

(W/VPP) Low

●

or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write

Protect/ (W/VPP) High.

If Write Protect/ (W/VPP) is permanently tied High, the Hardware Protected Mode (HPM) can

never be activated, and only the Software Protected Mode (SPM), using the Block Protect

(BP2, BP1, BP0) bits of the Status Register, can be used.

Figure 12.

Write Status Register (WRSR) instruction sequence

AI02282D

3456789 10 11 12 13 14 15

High Impedance

Instruction

Status

765432

MSB

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