STA323W datasheet(21/41 Pages) STMICROELECTRONICS

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STA323W

7.7.3 Binary Clock Loss Detection Enable

Detects loss of input MCLK in binary mode and will output 50% duty cycle to prevent audible artifacts when

input clocking is lost.

7.7.4 Auto-EAPD on Clock Loss Enable

When ECLE is active, it issues a power device power down signal (EAPD) on clock loss detection.

7.7.5 External Amplifier Power Down

EAPD is used to actively power down a connected DDX® Power device. This register has to be written to

1 at start-up to enable the DDX® power device for normal operation.

7.8 VOLUME CONTROL

7.8.1 Master Controls

7.8.1.1Master Mute Register (Address 06h)

7.8.1.2Master Volume Register (Address 07h)

Note : Value of volume derived from MVOL is dependent on AMV AutoMode Volume settings.

7.8.2 Channel Controls

7.8.2.1Channel 1 Volume (Address 08h)

BIT

R/W

RST

NAME

DESCRIPTION

R/W

BCLE

Binary Output Mode Clock Loss Detection Enable

0 – Disabled

1 – Enabled

BIT

R/W

RST

NAME

DESCRIPTION

R/W

ECLE

Auto EAPD on Clock Loss

0 – Disabled

1 – Enabled

BIT

R/W

RST

NAME

DESCRIPTION

R/W

EAPD

External Amplifier Power Down:

0 – External Power Stage Power Down Active

1 – Normal Operation

MMUTE

MV7

MV6

MV5

MV4

MV3

MV2

MV1

MV0

C1V7

C1V6

C1V5

C1V4

C1V3

C1V2

C1V1

C1V0

1000

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