ST7L15 datasheet(84/138 Pages) STMICROELECTRONICS

84 / 138 page

ST7L15, ST7L19

84/138

SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.6 Low Power Modes

11.4.6.1 Using the SPI to wake up the device

from Halt mode

In slave configuration, the SPI is able to wake up

the device from HALT mode through a SPIF inter-

rupt. The data received is subsequently read from

the SPIDR register when the software is running

(interrupt vector fetch). If multiple data transfers

have been performed before software clears the

SPIF bit, then the OVR bit is set by hardware.

Note: When waking up from HALT mode, if the

SPI remains in Slave mode, it is recommended to

perform an extra communications cycle to bring

the SPI from HALT mode state to normal state. If

the SPI exits from Slave mode, it returns to normal

state immediately.

Caution: The SPI can wake up the device from

HALT mode only if the Slave Select signal (exter-

nal SS pin or the SSI bit in the SPICSR register) is

low when the device enters HALT mode. So, if

Slave selection is configured as external (see Sec-

tion 11.4.3.2), make sure the master drives a low

level on the SS pin when the slave enters HALT

mode.

11.4.7 Interrupts

Note: The SPI interrupt events are connected to

the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the interrupt mask in

the CC register is reset (RIM instruction).

Mode

Description

WAIT

No effect on SPI.

SPI interrupt events cause the device to exit

from WAIT mode.

HALT

SPI registers are frozen.

In HALT mode, the SPI is inactive. SPI oper-

ation resumes when the device is woken up

by an interrupt with “exit from HALT mode”

capability. The data received is subsequently

read from the SPIDR register when the soft-

ware is running (interrupt vector fetching). If

several data are received before the wake-

up event, then an overrun error is generated.

This error can be detected after the fetch of

the interrupt routine that woke up the Device.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

SPI End of

Transfer Event

SPIF

SPIE

Yes

Master Mode

Fault Event

MODF

Overrun Error

OVR

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