UPD61052GD-LML datasheet(13/108 Pages) RENESAS

13 / 108 page

Data Sheet S15082EJ4V0DS

µPD61051, 61052

1.6

Stream Output Interface

This interface outputs MPEG TS/PS stream. When in master mode (MPEG2-TS output with using valid signal),

data output is possible to select 8bits parallel data or serial data mode. In serial mode, data output from OS0.

Active polarity of OSVLD is selected by the port setup register.

Active polarity of OSCLK/OSSTB and OSSYNC are selected by firmware. These are unsettled after the turning on.

Name

Number

Function

Active

Polarity

OSREQ

Stream data request in slave mode

OSCLK/OSSTB

Stream data strobe

After reset, default is active high edge.

OSCLK/OSSTB

Stream data clock

After reset, default is OSSTB.

OSSYNC

Stream data synchronization

After reset, default is active high.

OSVLD/OSRDY

Stream data valid

After reset, default is OSRDY.

OSVLD/OSRDY

Stream data ready prepared

After reset, default is active low.

OS7 to OS0/

FA13 to FA6

65 to 63,

61, 59 to

Stream data output

Remark

In this table, means of reset are hardware reset by the RESET pin and ALL RESET of the reset register.

1.7

SDRAM Interface

Name

Pin Number

Function

Active

Polarity

MA13 to MA0

104, 103, 115, 102, 114, 113, 111,

109, 108, 106, 101, 99, 97, 95

Address of row/column

MD31 to MD0

93 to 89, 87, 85, 83, 72, 75 to 81,

149, 147 to 143, 141, 139, 127,

129, 131 to 134, 136, 138

Data

(Built-in 50 k

Ω pull up resistor)

MCLK

118

Clock

↑

MCKE

116

Clock enable

MCS

120

Chip selection

MRAS

121

Row address strobe

MCAS

123

Column address strobe

MWE

125

Write enable

MDQM

126

Data input/output mask enable

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