Data Sheet S17102EJ2V0DS

19

µ PD16908

8.3 Serial Correspondence Timing

SDA

MSB

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

LSB

Read at the rising

High-level load

SCL

CS

• The 12-bit serial data inputted by the SDA pin is loaded to the shift register at the rising edge of the signal inputted to

the SCL pin. The loaded data is loaded to the shift register at the rising edge of the signal inputted to the CS pin.

Be sure to fix the signal input to the SCL pin to low level at the rising and falling edges of the signal input to the CS

pin.

• If the data which is loaded to shift register while the CS pin is low level is less than 12 bits, the loaded data is

cancelled. If the loaded data is more than 12 bits, the 12-bit data is valid in the last of the loaded data.