STM32MP153F datasheet(33/38 Pages) ETC

33 / 38 page

OSD32MP15x Datasheet

Rev. 7 11/30/2022

Octavo Systems LLC

The VDD Pins are separated into two (2) logical groups in the ball map. Each pin in the

respective group must be connected to the other pins in that same group. The two

groups do not need to be connected to each other. Specifically Pins M4, L4, and K4

must be connected together and Pins M7, L7, K7, J7, H7, and G7 must be connected

together.

7.6.4 VTT_DDR

VTT_DDR is generated by LDO3 in the STPMIC1A. It provides power to the DDR VTT. By

default, its voltage is 1.8V. See Table 7-1 for required STPMIC1A configuration of this voltage

rail.

7.6.5 VDD3V3_USB

VDD3V3_USB is generated by LDO4 in the STPMI1A. It provides power for the VDD_USB

power domain of the STM32MP15x. By default, its voltage is 3.3V. See Table 7-1 for required

STPMIC1A configuration of this voltage rail.

7.6.6 VREF_DDR

VREF_DDR is generated by VREFDDR in the STPMI1A. It provides power for the reference

voltage for the integrated DDR. By default, its voltage is 0.55V. See Table 7-1 for required

STPMIC1A configuration of this voltage rail.

7.6.7 VDD1V2_DSI_REG

VDD1V2_DSI_REG is generated by the VDDA1V2_DSI_REG regulator in the STM32MP15x. It is

connected internally within the OSD32MP15x to VDD1V2_DSI_PHY. Its voltage is 1.2V.

7.6.8 VDDA1V1_REG

VDDA1V1_REG is generated by the VDDA1V1_REG regulator in the STM32MP15x. Its voltage is

1.1V.

7.6.9 VDDA1V8_REG

VDDA1V8_REG is generated by the VDDA1V8_REG regulator in the STM32MP15x. It is connected

internally within the OSD32MP15x to VDDA1V8_DSI. Its voltage is 1.8V.

STM32MP153F bảng dữ liệu(PDF) 33 Page - List of Unclassifed Manufacturers