TPIC5423L

4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL

POWER DMOS ARRAY

SLIS045 – NOVEMBER 1994

2–5

POST OFFICE BOX 655303

Pulse Generator

50

Ω

Rgen

50

Ω

VGS

VDD = 25 V

DUT

VDS

TEST CIRCUIT

VDD

VDS(on)

tf

td(on)

tr

td(off)

VOLTAGE WAVEFORMS

VGS

VDS

RL

CL = 30 pF

(see Note A)

tdis

ten

5 V

0 V

NOTE A: CL includes probe and jig capacitance.

Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms

5 V

VOLTAGE WAVEFORM

Qgd

Time

Gate Voltage

VGS

12 V

Battery

0.2

µF

50 k

Ω

0.3

µF

Current

Regulator

DUT

Same Type

as DUT

0

IG = 100 µA

IG Current-

Sampling Resistor

ID Current-

Sampling Resistor

VDD

TEST CIRCUIT

Qgs(th)

VDS

Qg

Figure 3. Gate-Charge Test Circuit and Voltage Waveform