LXT971ABC datasheet(70/90 Pages) INTEL

70 / 90 page

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

Figure 40. Power-Up Timing

Table 39. Power-Up Timing Parameters

Parameter

Symbol

Min

Typ1

Max

Units

Test Conditions

Voltage threshold

–

2.9

–

Power Up delay2

–

300

µs–

1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production

testing.

2. Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance -

the PHY comes out of reset after a delay of No MORE Than 300

µs. System designers should consider this

as a minimum value - After threshold v1 is reached, the MAC should delay No LESS Than 300

µs before

accessing the MDIO port.

Figure 41. RESET Pulse Width and Recovery Timing

Table 40. RESET Pulse Width and Recovery Timing Parameters

Parameter

Symbol

Min

Typ1

Max

Units

Test Conditions

RESET pulse width

–

RESET recovery delay2

–

300

µs–

1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production

testing.

2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed

performance - the PHY comes out of reset after a delay of No MORE Than 300

µs. System designers

should consider this as a minimum value - After de-asserting RESET*, the MAC should delay No LESS

Than 300

µs before accessing the MDIO port.

VCC

MDIO,etc

RESET

MDIO,etc

LXT971ABC bảng dữ liệu(PDF) 70 Page - Intel Corporation

LXT971ABC bảng dữ liệu(HTML) 70 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

bảng dữ liệu tải về

Link URL