Figure 7-4. Write Cycle Timing

t

WR

Stop

Condition

Start

Condition

Data Word n

ACK

D0

SDA

Stop

Condition

SCL

8

9

ACK

First Acknowledge from the device

to a valid device address sequence after

write cycle is initiated. The minimum t

WR

can only be determined through

the use of an ACK Polling routine.

9

7.5

Write Protection

The AT24CS32 utilizes a hardware data protection scheme that allows the user to write‑protect the entire memory

contents when the WP pin is at VCC (or a valid VIH). No write protection will be set if the WP pin is at GND or left

floating.

Table 7-1. AT24CS32 Write-Protect Behavior

WP Pin Voltage

Part of the Array Protected

VCC

Full Array

GND

None － Write Protection Not Enabled

The status of the WP pin is sampled at the Stop condition for every byte write or page write operation prior to the start

of an internally self‑timed write cycle. Changing the WP pin state after the Stop condition has been sent will not alter

or interrupt the execution of the write cycle.

If an attempt is made to write to the device while the WP pin has been asserted, the device will acknowledge the

device address, word address and data bytes, but no write cycle will occur when the Stop condition is issued. The

device will immediately be ready to accept a new read or write command.

AT24CS32

Write Operations

© 2020 Microchip Technology Inc.

Datasheet

DS20006341A-page 20