CDCD5704 datasheet(9/17 Pages) TI

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RECOMMENDED AC OPERATING CONDITIONS

DEVICE CHARACTERISTICS

CDCD5704

SCAS823 – DECEMBER 2006

MIN

NOM

MAX

UNIT

tCYCLE,IN

REFCLK/REFCLKB input cycle time

tCYC,TEST REFCLK/REFCLKB input cycle time for BYPASS

tJ,IN

Input |cycle-to-cycle| jitter(1)

185

DCIN

Input duty cycle over 10,000 cycles(2)

40%

60%

tr/tf

Rise and fall time for REFCLK signal from 20% to 80% of input voltage VIN

175

700

tcr/tcf

Difference between rise time and fall time of REFCLK signal from 20% to 80%

150

fm,IN

SSC frequency modulation repeat frequency(3)

kHz

Pm tria

Modulation index (= frequency deviation/center frequency) for triangle modulation(3)

0.6%

Pm n tria

Modulation index (= frequency deviation/center frequency) for non-triangle modulation(4)

0.5%

tSR

Input slew rate REFCLK/REFCLKB

V/ns

SERIAL INTERFACE TIMING

fSCLK

SCLK frequency(5)

100

kHz

th(START)

START hold time(5)

µs

tw(SCLL)

SCLK low-pulse duration(5)

4.7

µs

tw(SCLH)

SCLK high-pulse duration(5)

µs

tsu(START) START setup time(5)

4.7

µs

th(SDATA)

SDATA hold time(5)

300

tsu(SDATA) SDATA setup time(5)

250

tr(SDATA)/

SDATA/SCLK input rise time(5)

1000

tr(SM)

tf(SDATA)/

SDATA/SCLK input fall time(5)

300

tf(SM)

tsu(STOP)

STOP setup time(5)

µs

t(BUS)

Bus free time

4.7

µs

(1)

RefCLK jitter is measured at (VIH(nom) – VIL(nom))/2 and is the absolute value of the worst-case deviation.

(2)

Measured at crossing points for differential clock input or at input threshold voltage VTH for single-ended clock input.

(3)

If input modulation is used; input modulation is allowed but not required.

(4)

The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which

cannot exceed the skew generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular

modulation is about 0.5%.

(5)

See Figure 1 for the timing behavior of the serial interface.

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OVERALL PARAMETER

At 300 MHz and 2.625 V

IDD

Supply current (= IVDD + IVDDP + IVDDC)

At 667 MHz and 2.625 V

115

Supply voltage threshold for power-up control

Over complete supply voltage

VPUC

1.1

1.8

2.2

circuit

range

DC DEVICE CHARACTERISTICS

VOX

Differential output crossing-point voltage(1)

Output load; see Figure 3.

0.9

1.1

VCOS

Output voltage swing (p-p, single-ended)(2)

0.3

0.325

0.35

VOL,ABS

Absolute output low voltage(3)

0.85

Reference voltage for swing control current

VDD = 2.375 V to 2.625 V, T = 0°C

VISET

0.98

1.02

IREF(4)

to 70

°C

(1)

VOX is measured on external divider as shown in Figure 3.

(2)

VCOS = (clock output high voltage – clock output low voltage), at the measurement points shown in Figure 3, excluding overshoot and

undershoot.

(3)

VOL,ABS is measured at the clock output of the package, instead of the measurement points of Figure 3.

(4)

IREF is equal to VISET/RRC. Tolerance of RRC must be ±1% or smaller.

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