3

AT90SP0801

1495AS–01/02

Serial Interface

Data is transferred to or from the I/O buffer on the chip using the SMBus interface, in a

manner similar but not identical to that of standard two-wire serial EEPROMs.

All bits are sent to or read from the chip most significant bit first, in a manner consistent

with standard serial EEPROMs. Bit fields listed in this document are correspondingly

listed with the MSB on the left and the LSB on the right. Hex numbers are specified with

the “0x” prefix.

Multi-byte information sent to the chip is sent most significant byte first, following typical

conventions. Within the chip, the first byte sent to the chip is stored in memory at the

lowest address, and the address is incremented for subsequent bytes. When a mes-

sage digest (hash) is sent to the chip, the first byte of the hash value is the first byte to

be sent to the chip.

In both the text and graphics, the chip is the slave and the system is the master. The fol-

lowing abbreviations apply:

For the graphical representations, the direction of the data flow is indicated as below:

SMBus Standard Usage

Data transfer to and from the chip follows the SMBus V1.1 standard, using only some of

the command protocols.

The “write” command of this chip uses the “Block Write” protocol of the SMBus spec.

Note that in this chip the count value can exceed 32. This chip does not support the

“Write Byte” and “Write Word” protocols of the SMBus spec.

The “Read” command of this chip uses the “Block Read” protocol of the SMBus spec.

Note that in this chip the “Read” command can be optionally executed without the pre-

ceding partial block write command. This chip does not support the “Receive Byte”,

“Read Byte” and “Read Word” protocols of the SMBus spec.

All other commands of this chip use the “Send Byte” protocol of the SMBus spec. Note

that the “Quick Command” and “Process Call” protocols of the SMBus spec are not sup-

ported by this chip.

Two-wire Serial EEPROM

Comparison

Some of the differences between this chip and a standard two-wire serial EEPROM are:

1.

The slave address of this chip is different from the A0-AF (hex) standard for

EEPROMs.

2.

The maximum clock rate is 100 kHz and Tdh is 300 ns. These specs are part of

SMbus.

3.

The supply voltage is 3.0V to 3.7V.

4.

The read address is not specified in the aborted read command.

5.

Multi-byte reads and writes are preceded by the number of bytes that will be

transferred.

A

Acknowledge (bus pulled low, master or slave)

N

Not Acknowledge (bus left high, master or slave)

S

Start (High-to-low on SDA with SCL high, master)

P

Stop (Low-to-high on SDA with SCL high, master)

Slave to Master

(Chip to System)

Master to Slave

(System to Chip)