MIC4606 datasheet(7/40 Pages) MICROCHIP

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DS20005604D-page 7

MIC4606

2.0

TIMING DIAGRAMS

2.1

Non-Overlapping LI/HI Input Mode

(MIC4606-1)

In LI/HI Input mode, external xLI/xHI inputs are delayed

to the point that xHS is low before xLI is pulled high and

similarly, xLO is low before xHI goes high.

xHO goes high with a high signal on xHI after a typical

delay of 35 ns (tHPLH). xHI going low drives xHO low

also with a typical delay of 35 ns (tHPHL).

Likewise, xLI going high forces xLO high after a typical

delay of 35 ns (tLPLH) and xLO follows the low transition

of xLI after a typical delay of 35 ns (tLPHL).

xHO and xLO output rise and fall times (tR/tF) are

typically 20 ns, driving 1000 pF capacitive loads.

All propagation delays are measured from the 50%

voltage level and rise/fall times are measured 10% to

90%.

FIGURE 2-1:

Separate Non-Overlapping

LI/HI Input Mode (MIC4606-1).

2.2

Overlapping LI/HI Input Mode

(MIC4606-1)

When xLI/xHI input high conditions overlap, xLO/xHO

output states are dominated by the first output to be

turned on. If xLI goes high (on) while xHO is high, xHO

stays high until xHI goes low. After a delay of tHOOFF,

and when xHS < 2.2V, xLO goes high with a delay of

tLOON. If xHS never trips the aforementioned internal

comparator reference (2.2V), a falling xHI edge

delayed by a typical 250 ns will set the “HS latch”,

allowing xLO to go high.

If xHS falls very fast, xLO will be held low by a 35 ns

delay, gated by HI going low. Conversely, xHI going

high (on) when xLO is high has no effect on the outputs

until xLI is pulled low (off) and xLO falls to < 1.9V. Delay

from xLI going low to xLO falling is tLOOFF and delay

from xLO < 1.9V to xHO being on is tHOON.

FIGURE 2-2:

Separate Overlapping LI/HI

Input Mode (MIC4606-1).

2.3

PWM Input Mode (MIC4606-2)

A low xPWM signal applied to the MIC4606-2 causes

the xHO to go low, typically to 35 ns (tHOOFF) after the

xPWM input goes low. At this point, the switch node

xHS falls (1-2).

When the xHS reaches 2.2V (VSWTH), the external

high-side MOSFET is deemed off and the xLO goes high,

typically within 35 ns (tLOON) (3-4). The xHS falling below

2.2V sets a latch that can only be reset by the xPWM

going high. This design prevents ringing on xHS from

causing an indeterminate xLO state. Should xHS never

trip the aforementioned internal comparator reference

(2.2V), a falling xPWM edge delayed by 250 ns will set the

“HS latch”, allowing xLO to go high. An 80 ns delay, gated

by xPWM going low, may determine the time to xLO going

high for fast falling HS designs. xPWM going high forces

xLO low in typically 35 ns (tLOOFF) (5-6).

tLPLH

tLPHL

tHPLH

tHPHL

xHS

xHO

xLO

xHI

xLI

tLOOFF

tHOOFF

tLOON

tHOON

xHS

xHO

xLO

xHI

xLI

2.2V

(typ)

1.9V

(typ)

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