MCP3910 datasheet(58/90 Pages) MICROCHIP

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MCP3910

DS20005116D-page 58

 2012-2020 Microchip Technology Inc.

7.4

Watchdog Timer Reset, Resetting

the Part in Two-Wire Mode

When the part has entered the Two-Wire mode, the

Hard Reset mode functionality is not available because

the RESET pin becomes the logic input for OSR0. If the

user wants to execute a full Reset of the part without

doing a POR, the Two-Wire mode incorporates an

internal Watchdog Timer that automatically performs a

full Reset of the part if the timer has elapsed.

The Watchdog Timer starts synchronously with each

rising edge of SCK/MCLK. If the SCK logic high state is

maintained for a time that is larger than tWATCH, the

Watchdog Timer circuit forces the full Reset of the chip,

which then returns to its default configuration with all

ADCs being reset. If the SCK logic high state is main-

tained for a time shorter than tWATCH and then

SCK/MCLK toggles to logic low, the internal timer is

cleared, waiting for another rising edge to restart.

The Watchdog Timer functionality induces a restriction

in the usable range of frequencies on SCK/MCLK. In

order to avoid intermittent Resets in all cases, the min-

imum SCK/MCLK frequency in Two-Wire Interface

mode is equal to the inverse of the minimum tWATCH

time (1/(2 x 3.6 µs) = 138.9 kHz if the duty cycle of the

SCK/MCLK is 50%).

The Watchdog Timer starts only on the rising edge of

SCK/MCLK, not on the falling edge. Maintaining

SCK/MCLK at a logic low state for large periods of time

does not create any Watchdog Timer Resets. A Watch-

dog Timer Reset is created only when the SCK/MCLK

state is maintained logic high during a long enough

period of time.

This Watchdog Timer period permits exiting the

Two-Wire Interface mode, if desired, by toggling the

OSC2/MODE pin to logic low before creating the

Watchdog Timer Reset and by maintaining it logic low

until the Reset happens.

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