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CS5016 bảng dữ liệu(PDF) 26 Page - Cirrus Logic

tên linh kiện CS5016
Giải thích chi tiết về linh kiện  16, 14 & 12-Bit, Self-Calibrating A/D Converters
PDF  46 Pages
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nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5016 bảng dữ liệu(HTML) 26 Page - Cirrus Logic

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background image
ures 21 and 23 show FFT plots computed from
an ideal 14 and 16-bit sinewave multiplied by a
Blackman-Harris window. Artifacts of window-
ing are discarded from the signal-to-noise
calculation using the assumption that quantization
noise is white. All FFT plots in this data sheet
were derived by averaging the FFT results from
ten 1024 point time records. This filters the spec-
tral variability that can arise from capturing finite
time records without disturbing the total energy
outside the fundamental. All harmonics which ex-
ist above the noise floor and the -92 dB
side-lobes from the Blackman-Harris window are
therefore clearly visible in the plots. For more in-
formation on FFT’s and windowing refer to: F.J.
HARRIS, "On the use of windows for harmonic
dc
50.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
Sampling Rate: 100kHz
Full Scale: 9Vp-p
S/N+D: 72.9dB
Input Frequency (kHz)
12.0
Signal
Amplitude
Relative to
Full Scale
(dB)
Figure 20. FFT Plot of CS5012A with 12 kHz
Full-Scale Input
dc
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
Input Frequency
Signal
Amplitude
Relative to
Full Scale
(dB)
S/N+D: 73.9 dB
f /2
s
Figure 18. Plot of Ideal 12-bit ADC
dc
50.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
Input Frequency (kHz)
1.0
Signal
Amplitude
Relative to
Full Scale
(dB)
Sampling Rate: 100kHz
Full Scale: 9Vp-p
S/N+D: 73.6dB
Figure 19. Plot of CS5012A with 1 kHz
Full Scale Input
Signal
Amplitude
Relative to
Full Scale
dc
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB
28 kHz
1 kHz
Sampling Rate: 56 kHz
Full Scale: 9V p-p
S/(N+D): 85.3 dB
Input Frequency
Figure 22. CS5014 FFT plot with 1 kHz
Full Scale Input
Signal
Amplitude
Relative to
Full Scale
dc
Input Frequency
S/(N+D): 86.1 dB
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB
f /2
s
Figure 21. Plot of Ideal 14-bit ADC
CS5012A, CS5014, CS5016
2-32
DS14F6



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