Nexperia

74ALVC573

Octal D-type transparent latch; 3-state

aaa-032675

74ALVC573

Transparent top view

GND(1)

Q7

D6

D7

Q6

D5

Q5

D4

Q4

D3

Q3

D2

Q2

D1

Q1

D0

Q0

9

12

8

13

7

14

6

15

5

16

4

17

3

18

2

19

terminal 1

index area

(1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered,

the solder land should remain floating or connected to GND.

Fig. 8. Pin configuration SOT764-1 (DHVQFN20)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

D0, D1, D2, D3, D4, D5, D6, D7

2, 3, 4, 5, 6, 7, 8, 9

data input

LE

11

latch enable input (active HIGH)

OE

1

output enable input (active LOW)

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7

19, 18, 17, 16, 15, 14, 13, 12

3-state latch output

VCC

20

supply voltage

GND

10

ground (0 V)

6. Functional description

Table 3. Functional table

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;

Z = High-impedance OFF-state.

Input

Output

Operating modes

OE

LE

Dn

Internal latch

Qn

L

H

L

L

L

Enable and read register

(transparent mode)

L

H

H

H

H

L

L

l

L

L

Latch and read register

L

L

h

H

H

H

L

l

L

Z

Latch register and disable

outputs

H

L

h

H

Z

74ALVC573

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 4 — 30 April 2021

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