14

µPD6P4B

Data Sheet U13594EJ2V1DS00

3.3 Program Memory Reading Procedure

(1)

Pull down the pins not used to GND via resistor. Keep the CLK pin low.

(2)

Supply 5 V to the VDD pin. Keep the VPP pin low.

(3)

Supply 5 V to the VPP pin after waiting for 10

µs.

(4)

Wait for 2 ms until oscillation of the ceramic resonator connected across the XIN and XOUT pins stabilizes.

(5)

Set the program memory address 0 clear mode by using the mode setting pins.

(6)

Supply 6 V to VDD and 12.5 V to VPP.

(7)

Set the program inhibit mode.

(8)

Set the verify mode. Data of each address is output sequentially each time the clock pulse is input to

the CLK pin four times.

(9)

Set the program inhibit mode.

(10) Set the program memory address 0 clear mode.

(11) Change the voltage on the VDD and VPP pins to 5 V.

(12) Turn off power.

The following figure illustrates steps (2) through (10) above.

Reset

Oscillation stabilization

wait time

Hi-Z

Hi-Z

VPP

VDD

GND

VDD+1

VDD

GND

CLK

VPP

VDD

D0-D7

MD0

MD1

MD2

MD3

Data output

Data output

"L"