ADS5546 datasheet(39/50 Pages) TI

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Digital Output Information

Output Interface

DDR LVDS Outputs

S0169-01

CLKOUTP

D0_D1_P

D2_D3_P

D4_D5_P

D6_D7_P

D8_D9_P

D10_D11_P

D12_D13_P

OVR

Pins

OutputClock

DataBitsD0.D1

DataBitsD2,D3

DataBitsD4,D5

DataBitsD6,D7

DataBitsD8,D9

DataBitsD10,D11

DataBitsD12,D13

Out-of-RangeIndicator

CLKOUTM

D0_D1_M

D2_D3_M

D4_D5_M

D6_D7_M

D8_D9_M

D10_D11_M

D12_D13_M

ADS5546

SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006

ADS5546 provides 14-bit data, an output clock synchronized with the data and an out-of-range indicator that

goes high when the output reaches the full-scale limits. In addition, output enable control (OE pin 7) is provided

to power down the output buffers and put the outputs in high-impedance state.

Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be

selected using the DFS (see Table 6) or the serial interface register bit <ODI>.

In this mode, the 14 data bits and the output clock are available as LVDS (Low Voltage Differential Signal)

levels. Two successive data bits are multiplexed and output on each LVDS differential pair as shown in

Figure 51. So, there are 7 LVDS output pairs for the 14 data bits and 1 LVDS output pair for the output clock.

Figure 51. DDR LVDS Outputs

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