Nexperia

74ALVT162821

20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aae331

VEXT

VCC

VI

VO

DUT

CL

RT

RL

RL

G

Test data is given in Table 9.

Definitions test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = Test voltage for switching times.

Fig. 9. Test circuit for measuring switching times

Table 9. Test data

Input

Load

VEXT

VI

fi

tW

tr, tf

CL

RL

tPHZ, tPZH tPLZ, tPZL

tPLH, tPHL

3.0 V or VCC

whichever is less

≤ 10 MHz 500 ns

≤ 2.5 ns

50 pF

500 Ω

GND

6 V or VCC x 2 open

74ALVT162821

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2020. All rights reserved

Product data sheet

Rev. 5 — 19 October 2020

11 / 15