MPC8560CPXAPDB datasheet(104/108 Pages) FREESCALE

104 / 108 page

MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1

104

Freescale Semiconductor

Document Revision History

3.0

Table 1—Corrected MII management voltage reference

Section 2.1.2—New

Table 2—Corrected MII management voltage reference

Table 5—Removed ‘minimum’ column

Table 5—Added AVDD power table

Table 8—New

Table 9—New

Table 12—Added overshoot/undershoot note.

Figure 4—New

Table 15—Restated tMCKSKEW1 as tMCKSKEW, removed tMCKSKEW2; added speed-specifc minimum

values for 333, 266, and 200 MHz; updated tDDSHME values.

Updated chapter to reflect that GMII, MII and TBI can be run with 2.5V signalling.

Table 28—Added MDIO output valid timing

Table 30—Updated tLBIVKH1, tLBIXKH1, and tLBOTOT.

Table 31—New

Table 18, Table 20, Table 22—Updated clock reference

Table 33—Updated tTDIVKH

Table 34—Updated tTDKHOX

Added tables and figures for CPM I2C

Table 44—Updated tPCIVKH

Section 14.1— Changed minium height from 2.22 to 3.07 and maximum from 2.76 to 3.75

Table 53.—Updated MII management voltage reference and added note 20.

Section 16.2.4.1—Changed

JC from 0.3 to 0.8; changed die-junction temperature from 67° to 71°

Section 17.7—Added paragraph that begins “TSEC1_TXD[3:0]...”

3.1

Updated Table 4 and Table 5.

Added Table 6.

Added MCK duty cycle to Table 15.

Updated fMDC, tMDC, tMDKHDV, and tMDKHDX parameters in Table 28.

Added LALE to tLBKHOV3 parameter in Table 30 and Table 31, and updated Figure 17 and Figure 18.

Corrected active level designations of some of the pins in Table 53.

Updated Table 62.

Table 61. Document Revision History

Rev. No.

Substantive Change(s)

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