công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

DFBM-CS320 bảng dữ liệu(PDF) 4 Page - Delta Electronics, Inc.

tên linh kiện DFBM-CS320
Giải thích chi tiết về linh kiện  Wireless communication module compliant with Bluetooth TM Specification V2.0EDR
PDF  10 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  DELTA [Delta Electronics, Inc.]
Trang chủ  http://www.deltaww.com
Logo DELTA - Delta Electronics, Inc.

DFBM-CS320 bảng dữ liệu(HTML) 4 Page - Delta Electronics, Inc.

  DFBM-CS320 Datasheet HTML 1Page - Delta Electronics, Inc. DFBM-CS320 Datasheet HTML 2Page - Delta Electronics, Inc. DFBM-CS320 Datasheet HTML 3Page - Delta Electronics, Inc. DFBM-CS320 Datasheet HTML 4Page - Delta Electronics, Inc. DFBM-CS320 Datasheet HTML 5Page - Delta Electronics, Inc. DFBM-CS320 Datasheet HTML 6Page - Delta Electronics, Inc. DFBM-CS320 Datasheet HTML 7Page - Delta Electronics, Inc. DFBM-CS320 Datasheet HTML 8Page - Delta Electronics, Inc. DFBM-CS320 Datasheet HTML 9Page - Delta Electronics, Inc. Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 10 page
background image
Preliminary
DFBM-CS320
Data Sheet
May 18, 2005
Proprietary Information and Specifications are Subject to Change
External Reference Clock Input
The DFBM-CS320 RF local oscillator and internal digital clocks are derived from the reference
clock at DFBM-CS320 XTAL_IN input. This reference may be either an external clock or from a
crystal connected between XTAL_IN and XTAL_OUT.
The external clock can either be a digital level square wave or sinusoidal and this may be
directly coupled to XTAL_IN without the need for additional components. If the peaks of the
reference clock are below 0 V or above 1.8 V, it must be driven through a DC blocking capacitor
(~33pF) connected to XTAL_IN.
The external clock signal should meet the specifications as below table.
Min
Typ
Max
Frequency
7.5 MHz
16 MHz
40 MHz
Duty cycle
20 : 80
50 : 50
80 : 20
Edge Jitter (At Zero Crossing)
-
-
15ps rms
Signal Level
400mV pk-pk
-
1.8V *
* If the external clock is driven through a DC blocking capacitor then maximum allowable
amplitude is reduced from 1.8V to 800mV pk-pk.



Html Pages

1 2 3 4 5 6 7 8 9 10


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com