LTC4100 datasheet(17/24 Pages) LINER

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LTC4100

sn4100 4100is

OPERATIO

The Current DAC Block

The current DAC is a delta-sigma modulator which con-

trols the effective value of an external resistor, RSET, used

to set the current limit of the charger. Figure 7 is a

simplified diagram of the DAC operation. The delta-sigma

modulator and switch convert the ChargingCurrent() value,

received via the SMBus, to a variable resistance equal to:

1.25RSET/ChargingCurrent()/ILIM[x])

Therefore, programmed current is equal to:

(102.3mV/RSENSE) (ChargingCurrent()/ILIM[x]),

for ChargingCurrent() < ILIM[x].

When a value less than 1/16th of the maximum current

allowed by ILIM is applied to the current DAC input, the

current DAC enters a different mode of operation called

LOWI. The current DAC output is pulse width modulated

with a high frequency clock having a duty cycle value of

1/8. Therefore, the maximum output current provided by

the charger is IMAX/8. The delta-sigma output gates this

low duty cycle signal on and off. The delta-sigma shift

registers are then clocked at a slower rate, about 45ms/bit,

so that the charger has time to settle to the IMAX/8 value.

The resulting average charging current is equal to that

requested by the ChargingCurrent() value.

Note: The LOWI mode can be disabled by setting the

NO_LOWI bit in the LTC0() function.

When wake-up is asserted to the current DAC block, the

delta-sigma is then fixed at a value equal to 80mA, inde-

pendent of the ILIM setting.

Input FET

The input FET circuit performs two functions. It enables

the charger if the input voltage is higher than the CLP pin,

and provides an indication of this condition at both the

CHGEN pin and the PWR_FAIL bit in the ChargerStatus()

a low forward voltage drop when charging and prevents

reverse current flow through the input FET.

If the input voltage is less than VCLP, it must go at least

130mV higher than VCLP to activate the charger. The

CHGEN pin is forced low unless this condition is met. The

gate of the input FET is driven to a voltage sufficient to keep

a low forward voltage drop from drain to source. If the

voltage between DCIN and CLP drops to less than 25mV,

the input FET is turned off slowly. If the voltage between

DCIN and CLP is ever less than –25mV, then the input FET

is turned off quickly to prevent significant reverse current

from flowing in the input FET. In this condition the CHGEN

pin is driven low and the charger is disabled.

IPROG

(FROM CA1 AMP)

4100 F07

RSET

VREF

IDC

CHARGING_CURRENT

VALUE

ITH

∆-∑

MODULATOR

Figure 7. Current DAC Operation

ILIMIT/8

AVERAGE CHARGER CURRENT

4100 F08

~40ms

Figure 8. Charging Current Waveform in Low Current Mode

PROGRAMMED VALUE (V)

4100 F06

RVLIM = 33k

NOTE: THE LTC4100 CAN BE PROGRAMMED WITH ChargingVoltage() FUNCTION VALUES

BETWEEN 1.184V AND 2.9V, HOWEVER, THE BATTERY CHARGER CONTROLLER OUTPUT

VOLTAGE MAY BE ZERO WITH PROGRAMMED VALUES BELOW 2.9V.

Figure 6. Transfer Function of Charger

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