TMPR4925XB datasheet(17/32 Pages) TOSHIBA

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INTEGRATED CIRCUIT

TOSHIBA RISC PROCESSOR

TMPR4925XB

TENTATIVE

EJC-TMPR4925XB-17

26/Dec/01 Rev 0.1

TOSHIBA CORPORATION

External Bus Interface

Signal Name

Type

Function

Initial State

SYSCLK

Output

System Clock

Clock for external I/O devices.

Outputs a clock in full speed mode (at the same frequency as the G-Bus clock

(GBUSCLK) frequency), half speed mode (at one half the GBUSCLK frequency),

third speed mode (at one third the GBUSCLK frequency), or quarter speed mode (at

one quarter the GBUSCLK frequency). The boot configuration signals on the

ADDR[4:3] pins select which speed mode will be used.

When this clock signal is not used, the pin can be set to L using the SYSCLK Enable

bit of the configuration register (PCFG.SYSCLKEN).

High

UAE

Output

Upper Address Enable

Latch enable signal for the high-order address bits of ADDR. The enable polarity

can be selected.

This signal is also used as a boot configuration input signal for testing. Because

this signal is used for testing, ensure that it will not pulled Low during a reset

sequence. For details of configuration signals.

This signal is used as an input signal while the RESET* signal is asserted. It

becomes an output signal once the RESET* signal has been deasserted.

Input

CE[5:4]*

Output

Chip Enable

Chip select signals for ROM, SRAM, and I/O devices.

The pins are shared with other functions.

All High

CE[3:0]*

Output

Chip Enable

Chip select signals for ROM, SRAM, and I/O devices.

All High

OE*

Output

Output Enable

Output enable signal for ROM, SRAM, and I/O devices.

High

SWE*

Output

Write Enable

Write enable signal for SRAM and I/O devices.

High

BWE[3:0]*

/BE[3:0]*

Output

Byte Enable/Byte Write Enable

BE[3:0]* indicate a valid data position on the data bus DATA[31:0] during read and

write bus operation. In 16-bit bus mode, only BE[1:0]* are used. In 8-bit bus mode,

only BE[0]* is used.

BWE[3:0]* indicate a valid data position on the data bus DATA[31:0] during write

bus operation. In 16-bit bus mode, only BWE[1:0]* are used. In 8-bit bus mode, only

BWE[0]* is used.

The following shows the correspondence between BE[3:0]*/BWE[3:0]* and the

data bus signals.

BE[3]*/BWE[3]*:

DATA[31:24]

BE[2]*/BWE[2]*:

DATA[23:16]

BE[1]*/BWE[1]*:

DATA[15:8]

BE[0]*/BWE[0]*:

DATA[7:0]

The boot configuration signal on the ADDR[11] pin and the EBCCRn.BC bit of the

external bus controller determine whether the signals are used as BE[3:0]* or

BWE[3:0]*.

All High

ACK*/ READY

Input/out

put

Data Acknowledge/Ready

Flow control signal.

Input

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