EPCS64 datasheet(11/32 Pages) ALTERA

11 / 32 page

Altera Corporation

Core Version a.b.c variable

4–11

July 2004

Configuration Handbook, Volume 2

Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet

All attempts to access the memory contents while a write or erase cycle is

in progress will not be granted, and the write or erase cycle will continue

unaffected.

Write Enable Operation

The write enable operation code is

b'0000 0110, and the most

significant bit is listed first. The write enable operation sets the write

enable latch bit, which is bit 1 in the status register. Always set the write

enable latch bit before write bytes, write status, erase bulk, and erase

sector operations. Figure 4–5 shows the timing diagram for the write

enable operation. Figures 4–7 and 4–8 show the status register bit

definitions.

Table 4–8. Operation Codes for Serial Configuration Devices

Operation

Operation Code (1)

Address Bytes

Dummy Bytes

Data Bytes

DCLK fMAX

(MHz)

Write enable

0000 0110

Write disable

0000 0100

Read status

0000 0101

1 to infinite (2)

Read bytes

0000 0011

1 to infinite (2)

Read silicon ID

1010 1011

1 to infinite (2)

Write status

0000 0001

Write bytes

0000 0010

1 to 256 (3)

Erase bulk

1100 0111

Erase sector

1101 1000

Notes to Table 4–8:

(1)

The MSB is listed first and the least significant bit (LSB) is listed last.

(2)

The status register, data or silicon ID are read out at least once on the

DATA pin and will continuously be read out

until

nCS is driven high

(3)

Write bytes operation requires at least one data byte on the

DATA pin. If more than 256 bytes are sent to the device,

only the last 256 bytes are written to the memory.

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