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SCD5584A bảng dữ liệu(PDF) 12 Page - Infineon Technologies AG |
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SCD5584A bảng dữ liệu(HTML) 12 Page - Infineon Technologies AG |
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12 / 15 page ![]() 2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA SCD5580/1/2/3/4 A www.infineon.com/opto • 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany www.osram-os.com • +49-941-202-7178 12 March 23, 2000-18 Cascading Multiple Displays Multiple displays can be cascaded using the CLK SEL and CLK I/O pins as shown below. The display designated as the Master Clock source should have its CLK SEL pin tied high and the slaves should have their CLK SEL pins tied low. All CLK I/O pins should be tied together. One display CLK I/O can drive 15 slave CLK I/Os. Use RST to synchronize all display counters. Figure 14. Cascading Multiple Displays Loading Data Into the Display Use following procedure to load data into the display: 1. Power up the display. 2. Bring RST low (600 ns duration minimum) to clear the Multiplex Counter, Address Register, Control Word Register, User RAM and Data Register. The display will be blank. Display brightness is set to 100%. 3. If a different brightness is desired, load the proper brightness opcode into the Control Word Register. 4. Load the Digit Address into the display. 5. Load display row and column data for the selected digit. 6. Repeat steps 4 and 5 for all digits. RST CLK I/O CLK SEL DATA SDCLK LOAD 14 more displays in between RST CLK I/O CLK SEL DATA SDCLK LOAD Chip Address Decoder 0 15 Address Decode 1–14 VCC RST DATA SDCLK A0 A1 A2 A3 LD Intelligent Display Intelligent Display CE |
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