NE56632-29D datasheet(4/16 Pages) PHILIPS

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Philips Semiconductors

Product data

NE56632-XX

Active-LOW system reset with adjustable delay time

2002 Mar 25

ELECTRICAL CHARACTERISTICS

Tamb = 25 °C, unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

-XX

MIN.

TYP.

MAX.

UNIT

Detection threshold

VCC = HIGH-to-LOW; RL = 4.7 kΩ; S1=ON;

≤ 04 V

4.531

4.600

4.669

VOL ≤ 0.4 V;

Test Circuit 1 (Figure 27)

4.432

4.500

4.568

Test Circuit 1 (Figure 27)

4.334

4.400

4.466

4.235

4.300

4.365

4.137

4.200

4.263

3.053

3.100

3.147

2.955

3.000

3.045

2.856

2.900

2.944

2.758

2.800

2.842

2.659

2.700

2.741

1.970

2.000

2.030

1.871

1.900

1.929

Vhys

Hysteresis voltage

RL = 4.7 kΩ; VCC = LOW-to-HIGH-to-LOW; S1 = ON; Test

Circuit 1 (Figure 27)

100

VS/∆T

Detection threshold voltage

temperature coefficient

RL = 4.7 kΩ; Tamb = –20 °C to +75 °C; S1 = ON;

Test Circuit 1 (Figure 27)

–

±0.01

–

°C

VOL

LOW-level output voltage

VCC1 = VS(min) – 0.05 V; RL = 4.7 kΩ; S1 = ON;

Test Circuit 1 (Figure 27)

–

0.2

0.4

ILO

Output leakage current

VCC1 = VCC2 = 10 V; S2 = ON; Test Circuit 1 (Figure 27)

–

±0.1

µA

ICCL

Supply current (ON time)

VCC1 = VS(min) – 0.05 V; RL = ∞; Test Circuit 1 (Figure 27)

–

5.0

9.0

µA

ICCH

Supply current (OFF time)

VCC1 = VS(typ)/0.85; RL = ∞; Test Circuit 1 (Figure 27)

–

3.0

5.0

µA

tPLH

LOW-to-HIGH delay time

CL = 100 pF; RL = 4.7 kΩ; CD = 10 nF (Note 1)

–

(Note 3)

–

tPHL

HIGH-to-LOW delay time

CL = 100 pF; RL = 4.7 kΩ; CD = 10 nF (Note 2)

–

(Note 3)

–

µs

VOPL

Minimum operating

threshold voltage

RL = 4.7 kΩ; VOL ≤ 0.4 V; S1 = ON;

Test Circuit 1 (Figure 27)

–

0.65

0.80

IOL1

Output current (ON Time 1)

VO = 0.4 V; RL = 0; VCC1 = VS(min) – 0.05 V;

VCC2 = 0.4 V; S2 = ON; Test Circuit 1 (Figure 27)

–

IOL2

Output current (ON Time 2)

VO = 0.4 V; RL = 0; VCC1 = VS(min) – 0.05 V;

Tamb = –20 °C to +75 °C; S2 = ON;

Test Circuit 1 (Figure 27)

–

NOTES:

1. tPLH:VCC = (VS(typ) – 0.4 V) to (VS(typ) + 0.4 V); tPLH is release delay time (Test Circuit 2, Figure 28).

2. tPHL:VCC = (VS(typ) + 0.4 V) to (VS(typ) – 0.4 V); tPHL is assertion delay time (Test Circuit 2, Figure 28).

3. See Table 1.

Table 1. NE56632-XX series typical delay time

–XX

tPLH

tPHL

195 ms

140

µs

190 ms

140

µs

185 ms

140

µs

180 ms

140

µs

175 ms

140

µs

120 ms

120

µs

115 ms

120

µs

110 ms

120

µs

105 ms

100

µs

100 ms

100

µs

65 ms

100

µs

60 ms

100

µs

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