Nexperia

74LVC2G241

Dual buffer/line driver; 3-state

mna731

tPLZ

tPHZ

outputs

disabled

outputs

enabled

VY

VX

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

2OE input

VOL

VOH

VCC

VI

VM

GND

GND

tPZL

tPZH

VM

VM

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 7. Enable and disable times for input 2OE

VEXT

VCC

VI

VO

001aae235

DUT

CL

RT

RL

RL

PULSE

GENERATOR

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

Test data is given in Table 10.

Definitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance; RL = Load resistance.

Fig. 8. Test circuit for measuring switching times

Table 10. Test data

Input

Load

VEXT

Supply voltage

VI

CL

RL

tPLH, tPHL

tPZH, tPHZ

tPZL, tPLZ

1.65 V to 1.95 V VCC

30 pF

1 kΩ

open

GND

2 x VCC

2.3 V to 2.7 V

VCC

30 pF

500 Ω

open

GND

2 x VCC

2.7 V

2.7 V

50 pF

500 Ω

open

GND

6 V

3.0 V to 3.6 V

2.7 V

50 pF

500 Ω

open

GND

6 V

4.5 V to 5.5 V

VCC

50 pF

500 Ω

open

GND

2 x VCC

74LVC2G241

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©

Nexperia B.V. 2019. All rights reserved

Product data sheet

Rev. 16 — 31 July 2019

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