Nexperia

74LVC07A

Hex buffer with open-drain outputs

4. Functional diagram

mna535

2

1 1A

1Y

4

3 2A

2Y

6

5 3A

3Y

8

9 4A

4Y

10

11 5A

5Y

12

13 6A

6Y

Fig. 1. Logic symbol

mna534

1A

2A

3A

4A

5A

6A

1Y

2Y

3Y

4Y

5Y

6Y

2

1

1

4

3

6

5

8

9

10

11

12

13

1

1

1

1

1

Fig. 2. IEC logic symbol

mna533

GND

A

Y

Fig. 3. Logic diagram for one gate

5. Pinning information

5.1. Pinning

74LVC07A

1A

VCC

1Y

6A

2A

6Y

2Y

5A

3A

5Y

3Y

4A

GND

4Y

001aad066

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 4. Pin configuration for SOT108-1 (SO14) and

SOT402-1 (TSSOP14)

001aad067

74LVC07A

GND(1)

Transparent top view

3Y

4A

3A

5Y

2Y

5A

2A

6Y

1Y

6A

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 5. Pin configuration for SOT762-1 (DHVQFN14)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

1A, 2A, 3A, 4A, 5A, 6A

1, 3, 5, 9, 11, 13

data input

1Y, 2Y, 3Y, 4Y, 5Y, 6Y

2, 4, 6, 8, 10, 12

data output

GND

7

ground (0 V)

VCC

14

supply voltage

74LVC07A

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2020. All rights reserved

Product data sheet

Rev. 7 — 3 August 2020

2 / 12