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PCI7410

SLLA247 – JULY 2006

PC Card, UltraMedia™ and Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer

Controller

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Fully interoperable with FireWire™ and

i.LINK™ implementations of IEEE Std 1394

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PC Card Standard 8.0 compliant

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Compliant with Intel Mobile Power Guideline

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PCI Bus Power Management Interface

2000

Specification 1.1 compliant

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Full IEEE Std 1394a-2000 support includes:

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Advanced Configuration and Power Interface

connection debounce, arbitrated short reset,

(ACPI) Specification 2.0 compliant

multispeed concatenation, arbitration

•

PCI Local Bus Specification Revision 2.3

acceleration, fly-by concatenation, and port

compliant

disable/suspend/resume

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PC 98/99 and PC2001 compliant

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Power-down features to conserve energy in

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Compliant with the PCI Bus Interface

battery-powered applications include:

Specification for PCI-to-CardBus Bridges

automatic device power down during

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Fully compliant with provisions of IEEE Std

suspend, PCI power management for

1394-1995 for a high-performance serial bus

link-layer, and inactive ports powered down,

and IEEE Std 1394a-2000

ultralow-power sleep mode

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Fully compliant with 1394 Open Host

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Two IEEE Std 1394a-2000 fully compliant

Controller Interface Specification 1.1

cable ports at 100M bits/s, 200M bits/s, and

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1.8-V core logic and 3.3-V I/O cells with

400M bits/s

internal voltage regulator to generate 1.8-V

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Cable ports monitor line conditions for active

connection to remote node

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Universal PCI interfaces compatible with

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Cable power presence monitoring

3.3-V and 5-V PCI signaling environments

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Separate cable bias (TPBIAS) for each port

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Supports PC Card or CardBus with hot

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Physical write posting of up to three

insertion and removal

outstanding transactions

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Supports 132-MBps burst transfers to

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PCI burst transfers and deep FIFOs to

maximize data throughput on both the PCI

tolerate large host latency

bus and the CardBus

•

External cycle timer control for customized

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Supports serialized IRQ with PCI interrupts

synchronization

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Programmable multifunction terminals

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Extended resume signaling for compatibility

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Many interrupt modes supported

with legacy DV components

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Serial ROM interface for loading subsystem

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PHY-Link logic performs system initialization

ID and subsystem vendor ID

and arbitration functions

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ExCA-compatible registers are mapped in

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PHY-Link encode and decode functions

memory or I/O space

included for data-strobe bit level encoding

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Intel 82365SL–DF register compatible

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PHY-Link incoming data resynchronized to

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Supports ring indicate, SUSPEND, and PCI

local clock

CCLKRUN protocol and PCI bus Lock (LOCK)

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Low-cost 24.576-MHz crystal provides

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Provides VGA/palette memory and I/O, and

transmit and receive data at 100M bits/s,

subtractive decoding options, LED activity

200M bits/s, and 400M bits/s

terminals

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UltraMedia is a trademark of Texas Instruments.

FireWire is a trademark of Apple Computer, Inc..

i.LINK is a trademark of Sony Corporation of America.

PRODUCTION DATA information is current as of publication date.

Copyright © 2006, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.