PCA9574_V01 datasheet(15/29 Pages) NXP

15 / 29 page

NXP Semiconductors

PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

1 0 0 0 0 A0 1 A

S 0

target address

START condition

R/W acknowledge

from target

002aad060

data from port

acknowledge

from controller

SDA

no acknowledge

from controller

read from

port

data into

port

data from port

DATA 1

DATA 4

INT

DATA 4

DATA 2

DATA 3

STOP

condition

tv(INT)

trst(INT)

th(D)

tsu(D)

2 3 4 5 6 7 8

SCL

This figure assumes the command byte has previously been programmed with 00h.

Transfer of data can be stopped at any moment by a STOP condition.

Figure 14. Read Input port register

10 Application design-in information

PCA9574

SCL

SDA

VDD

SCL

SDA

VDD

VSS

CONTROLLER

VSS

VDD = 1.1 V to 3.6 V

SUBSYSTEM 1

(e.g., temp. sensor)

INT

SUBSYSTEM 2

(e.g., counter)

RESET

controlled switch

(e.g., CBT device)

enable

INT

VDD(IO)

INT

1.1 kΩ

2 kΩ

SUBSYSTEM 3

(e.g., alarm system)

ALARM

VDD(IO)

1.6 kΩ

RESET

VDD(IO) = 1.1 V to 3.6 V

002aad061

SUBSYSTEM 4

(e.g., RF module)

CTRL

Device address configured as 0100 0000b for this example.

P0, P2, P3 configured as outputs.

P1, P4, P5 configured as inputs.

P6, P7 are not used and must be configured as outputs.

Figure 15. Typical application

PCA9574

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6.0 — 31 May 2023

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