Data Sheet

AD9694S-CSL

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 13 of 16

Figure 5. Pin Configuration (Top View)

Table 12. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

0

AGND/EPAD

Ground

Exposed Pad. Analog Ground. The exposed thermal pad on the bottom of the

package provides the ground reference for AVDDx, SPIVDD, DVDD, DRVDD1,

and DRVDD2. This exposed pad must be connected to ground for proper

operation.

1, 6, 49, 54

AVDD3

Supply

Analog Power Supply (2.5 V Nominal).

2, 3

VIN−A, VIN+A

Input

ADC A Analog Input Complement/True.

4, 5, 9, 46, 50, 51, 55, 72

AVDD2

Supply

Analog Power Supply (1.8 V Nominal).

7, 8

VIN+B, VIN−B

Input

ADC B Analog Input True/Complement.

10, 11, 44, 45, 56, 57, 58, 59, 62, 68,

69, 70, 71

AVDD1

Supply

Analog Power Supply (0.975 V Nominal).

12

VCM_AB

Output

Common-Mode Level Bias Output for Analog Input Channel A and Channel B.

13, 42

DVDD

Supply

Digital Power Supply (0.975 V Nominal).

14, 41

DGND

Ground

Ground Reference for DVDD and SPIVDD.

15

DRVDD2

Supply

Digital Power Supply for JESD204B PLL (1.8 V Nominal).

16

PDWN/STBY

Input

Power-Down Input/Standby (Active High). The operation of this pin depends

on the SPI mode and can be configured as power-down or standby. This pin

requires external 10 kΩ pull-down resistor.

17, 18, 35, 36

FD_A, FD_B, FD_D, FD_C

Output

Fast Detect Outputs for Channel A, Channel B, Channel C, and Channel D.

19

SYNCINB−AB

Input

Active Low JESD204B LVDS Sync Input Complement for Channel A and

Channel B.

20

SYNCINB+AB

Input

Active Low JESD204B LVDS/CMOS Sync Input True for Channel A and

Channel B.

21, 32

DRGND

Ground

Ground Reference for DRVDD1 and DRVDD2.

22, 31

DRVDD1

Supply

Digital Power Supply for SERDOUTABx±/SERDOUTCDx± Pins (0.975 V

Nominal).

23, 24

SERDOUTAB0−,

SERDOUTAB0+

Output

Lane 0 Output Data Complement/True for Channel A and Channel B.

25, 26

SERDOUTAB1−,

SERDOUTAB1+

Output

Lane 1 Output Data Complement/True for Channel A and Channel B.

27, 28

SERDOUTCD1+,

SERDOUTCD1−

Output

Lane 1 Output Data True/Complement for Channel C and Channel D.