GTVA261802FC

6

Rev. 02.1, 2022-1-27

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The information in this document is subject to change without notice.

4600 Silicon Drive | Durham, NC 27703 | Tel: +1.919.313.5300

H-37248-4_pd_10-10-2012

S

D1

D2

G1

G2

Pin

Description

D1

Drain Device 1 (Main)

D2

Drain Device 2 (Peak)

G1

Gate Device 1(Main)

G2

Gate Device 2 (Peak)

S

Source (flange)

Pinout Diagram (top view)

Main

Peak

Components Information

Component

Description

Manufacturer

P/N

Input

C101, C102, C103, C104

Capacitor, 12 pF

ATC

ATC600F120JT250X

C105, C106

Capacitor, 100V, 4.7 µF

TDK Corporation

C4532X7S2A475M230KB

R101, R102

Resistor, 10 ohms

Panasonic Electronic Components

ERJ-8GEYJ100V

R103

Resistor, 50 ohms

Richardson

C16A50Z4

U1

Hybrid coupler

Anaren

X3C26P1-03S

Output

C201, C202

Capacitor, 0.5 pF

ATC

ATC600F0R5JT250X

C203, C204, C205, C206

Capacitor, 12 pF

ATC

ATC600F120JT250X

C207, C208, C209, C210, C211, C212

Capacitor, 100 V, 4.7 µF

TDK Corporation

C4532X7S2A475M230KB

C213, C214

Capacitor, 470 µF

Cornell Dubilier Electronics (CDE)

SEK471M050ST

R201

Resistor, 50 ohms

Richardson

C16A50Z4

U2

Hybrid coupler

Anaren

X3C26P1-03S

Bias Sequencing

Bias On

1. Ensure RF is turned off

2. Apply pinch-off voltage of –5 V to the gate

3. Apply nominal drain voltage

4. Bias gate to desired quiescent drain current

5. Apply RF

Bias Off

1. Turn RF off

2. Apply pinch-off voltage to the gate

3. Turn-off drain voltage

4. Turn-off gate voltage