CDB5451A datasheet(9/24 Pages) CIRRUS

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CDB5451A

DS458DB3

2.3.7.2. Acquisition

Referring to Figure 3, the CS5451A’s SCLK line is

used to clock the 8-bit serial-in/parallel-out shift-

and shifts it into the 8 output bits QA-QG. The

SCLK signal is also fed into the up/down counter

U6 and after every 8 SCLKs, the “QC” pin of U6 will

latch the QA-QG output bits of U6 into the 8-bit D-

Flip-Flop (U3). While this is happening, the soft-

ware monitors the “BUSY” signal (from the “QD”

pin of U6). BUSY is the critical handshake signal.

A rising

or falling transition on BUSY indicates to

the software that it is now time to collect another

byte of data from the latched output on U3.

After sixteen SCLKs, the PC software has acquired

two bytes (16 bits) which represents one data sam-

ple. The 4-bit up/down counter (U6) will roll over

after every 16 SCLKs. (Note that U6 is cleared by

the CS5451A’s FSO signal at the beginning of

each frame, which insures that the counter begins

the frame in the correct state--cleared). This se-

quence, which lasts for 16 SCLKs, is performed a

total of six times in order to obtain the six 16-bit

words from the CS5451A.

After the last 16-bit word is acquired, the software

recognizes that the end of a data frame has been

reached, and it will continue to wait for the next

transition on the “BUSY” line. This will not occur

until the first 8 SCLKs of the next frame are sent

from the CS5451A. Various other signals in Figure

3 (STRB, FEED, ACK, etc.) are not used during

data capture and are only used for testing (internal

use only).

2.3.8 Connecting the Eval Board to PC

The CDB5451A connects to the user’s IBM-com-

patible PC with the included 25-pin parallel port ca-

ble.

The user should not connect this cable

between the CDB5451A and the parallel port on

the PC until all of the header options in Table 2

have been set to appropriate settings and the

user has applied power to the CDB5451A. The

parallel cable attached to the CDB5451A Evalua-

tion Board at J17. After connecting the parallel

port cable between the PC and CDB5451A, the

user should always actuate (press down on) the

“RESET” switch (S1) at least one time before per-

forming any other evaluation activities.

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