CDB49300 datasheet(9/50 Pages) CIRRUS

9 / 50 page

CDB4923 CDB49300

DS262DB2

input ports of the DSP. These configuration allows

the user to drive signals on stake headers J11 and

J12 in order to operate the DSP as if it were part of

an embedded system. The user is responsible for

providing the appropriate clocking signals, control

signals, and data signals to the DSP in full external

mode, but the user only provides control signals in

exernal control mode.

In the external modes the audio output of the DSP

still drives the on-board DACs and digital transmit-

ters thus allowing the user to access the audio on

the analog and digital output connectors provided

by the CDB4923/300. The stake headers J11 and

J12 can be found in Figure 4.

All on-board clocks and data lines are routed

through the PLD (U11) in order to provide maxi-

mum flexibility in the evaluation of different sys-

tem configurations. The PLD will perform all +5 V

to +3.3 V/+2.5 V conversions between the DSP

and the +5 V parts with which it interacts by con-

figuring the I/O power jumper (J63). The system

can also be configured in an external interface de-

scribed above. The external modes are detailed in

Data Selection. All PLD modes are selected using

DIP switch S3. The PLD (U11) and switch S3 are

shown in Figure 7.

A specialized IC (U12), the MAX708, has been in-

cluded on the CDB4923/300 in order to generate a

system reset at power-up, when the digital power

begins to fail, and when the system reset button

(SW1) is depressed. This chip helps to insure con-

sistent operation on the board by providing a

200 ms reset pulse whenever activated.

5. DATA SELECTION

Data selection on the CDB4923/300 refers to the

routing of audio data, audio clocks, control data,

and control clocks. Because the PLD plays such a

crucial role in determining the routing and control

scheme, each data selection mode is also referred to

as a ‘PLD mode.’ It is important to note that Table

2, the PLD Mode table, is based directly upon the

version of the control PLD (U11) used on each par-

ticular board. Each PLD has a specific revision

code printed on its label. If your PLD version dif-

fers from the one described in this document, con-

tact the factory to determine which feature set is

provided with your board.

Analog

Output

Stereo

Analog In

Digital Output

Digital Input

Control

Interface

Patch Area

RESET

+3.3V

+2.5V

CS492x

CS493xx

OSC

PLD

CS8404A

CS4340

CS5334

CRD4923-MEM

CDB49300-MEM

Figure 1. External Memory Example

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