TOP245F datasheet(8/52 Pages) POWERINT

8 / 52 page

TOP242-250

1/02

Figure 10. Synchronization Timing Diagram.

PI-2637-060600

Oscillator

(SAW)

DMAX

Enable from

X, L or M Pin (STOP)

Time

CURRENT LIMIT (X) pin (Y, R or F package) or MULTI-

FUNCTION (M) pin (P or G package) and the rectified DC

high voltage bus, the current limit is reduced with increasing

line voltage, allowing a true power limiting operation against

line variation to be implemented. When using an RCD clamp,

this power limiting technique reduces maximum clamp

voltage at high line. This allows for higher reflected voltage

designs as well as reducing clamp dissipation.

The leading edge blanking circuit inhibits the current limit

comparator for a short time after the output MOSFET is turned

on. The leading edge blanking time has been set so that, if a

power supply is designed properly, current spikes caused by

primary-side capacitances and secondary-side rectifier reverse

recovery time should not cause premature termination of the

switching pulse.

The current limit is lower for a short period after the leading

edge blanking time as shown in Figure 52. This is due to

dynamic characteristics of the MOSFET. To avoid triggering

the current limit in normal operation, the drain current wave-

form should stay within the envelope shown.

Line Under-Voltage Detection (UV)

At power up, UV keeps TOPSwitch-GX off until the input line

voltage reaches the under voltage threshold. At power down,

UV prevents auto-restart attempts after the output goes out of

regulation. This eliminates power down glitches caused by

the slow discharge of large input storage capacitor present in

applications such as standby supplies. A single resistor

connected from the LINE-SENSE pin (Y, R or F package) or

MULTI-FUNCTION pin (P or G package) to the rectified DC

high voltage bus sets UV threshold during power up. Once the

power supply is successfully turned on, the UV threshold is

lowered to 40% of the initial UV threshold to allow extended

input voltage operating range (UV low threshold). If the UV

low threshold is reached during operation without the power

supply losing regulation the device will turn off and stay off

until UV (high threshold) has been reached again. If the power

supply loses regulation before reaching the UV low threshold,

the device will enter auto-restart. At the end of each auto-

restart cycle (S7), the UV comparator is enabled. If the UV high

threshold is not exceeded the MOSFET will be disabled during

the next cycle (see Figure 8). The UV feature can be disabled

independent of OV feature as shown in Figures 19 and 23.

Line Overvoltage Shutdown (OV)

The same resistor used for UV also sets an overvoltage thresh-

old which, once exceeded, will force TOPSwitch-GX output

into off-state. The ratio of OV and UV thresholds is preset at

4.5 as can be seen in Figure 11. When the MOSFET is off, the

rectified DC high voltage surge capability is increased to the

voltage rating of the MOSFET (700 V), due to the absence of

the reflected voltage and leakage spikes on the drain. A small

amount of hysteresis is provided on the OV threshold to

prevent noise triggering. The OV feature can be disabled

independent of the UV feature as shown in Figures 18 and 32.

Line Feed Forward with DC

MAX Reduction

The same resistor used for UV and OV also implements line

voltage feed forward which minimizes output line ripple and

reduces power supply output sensitivity to line transients. This

feed forward operation is illustrated in Figure 7 by the

different values of I

L (Y, R or F package) or IM (P or G Pack-

age). Note that for the same CONTROL pin current, higher

line voltage results in smaller operating duty cycle. As an added

feature, the maximum duty cycle DC

MAX is also reduced from

78% (typical) at a voltage slightly higher than the UV thresh-

old to 38% (typical) at the OV threshold (see Figures 7 and

11). Limiting DC

MAX at higher line voltages helps prevent trans-

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