AlGaAs SPST Non-Reflective PIN Diode Switch

Rev 2.0

MA4AGSW1A

6

ASSEMBLY INSTRUCTIONS

The following precautions should be observed to avoid damaging these chips.

CLEANLINESS

These chips should be handled in a clean environment. Clean die after solder die attach installation with care.

STATIC SENSITIVITY

These Devices are considered ESD Class1. Proper ESD techniques should be used when handling these devices.

GENERAL HANDLING

The protective polymer coating on the active areas of these die provides scratch and impact protection, particularly

for the metal air bridge, which contacts the diode’s anode. Die should primarily be handled with vacuum pickups,

MOUNTING TECHNIQUES

These AlGaAs devices are designed to be mounted with electrically conductive silver epoxy or with a solder that

does not excessively scavenge gold.

SOLDER DIE ATTACH

All die attach and bonding methods should be compatible with gold metal. Solders which do not excessively

scavenge gold, such as 80Au/20Sn or Sn62/Pb36/Ag2 are acceptable for usage. Do not expose die to a temperature

greater than 300

°C for more than 10 seconds.

ELECTRICAL CONDUCTIVE EPOXY DIE ATTACH

Assembly can be preheated to approximately 125

°C. Use a controlled thickness of approximately 2 mils for best

electrical and thermal conductivity. Cure epoxy as per manufacturer’s schedule. For extended cure times,

temperatures should be kept below 150

°C.

RIBBON/WIRE BONDING

Wedge thermo compression bonding or ball bonding may be used to attach gold ribbons or gold wires to bonding

pads. 1 Mil diameter gold wire or 1/4 x 3 mil sq. gold ribbons should be used for all RF ports for lower inductance

and best mmwave performance.

Successful Operation of the MA4AGSW1A Switch

One External Bias Network and One External D.C Return is required for successful operation of the MA4AGSW1A

Absorptive SPST AlGaAs PIN Diode Switch. The Backside Area of the Die is the RF and D.C. Return Ground

Plane. In the Low Loss State, the Series Diode is Forward Biased with -1.35V, - 10 mA, at “ D.C. Bias 1 ” and the

Match Diode is Reverse Biased at -1.35V, 0 mA at “ D.C. Bias B ”. In the Isolation State, both the Shunt Diode and

the Match Diode are Both Forward Biased at + 1.35 V, + 10 mA at “ D.C. Bias 1” and “ D.C. Bias B ”. This

Isolation State condition makes the Series Diode Reverse Biased by 1.35V. This Isolation State Results in a Good

50 Ω Match into Port J2 Only. The RF to D.C. Bias Truth table is shown in Table I. The Bias Network Design

should yield > 30 dB RF to DC Isolation.