CAV424

C/V-converter for single and differential capacitive input signals

July 2014 – Rev. 3.0

Page 8/14

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Then for the next quarter of a period the capacitances CM and CR are discharged with twice the charge cur-

rent (2·ICM and 2·ICR) until VCLAMP is reached. VCLAMP is held for the last quarter of the period. Afterwards this

cycle starts again.

3. Signal Processing Unit (Low Pass Filter and Output Stage)

To generate a single voltage from the measurement and reference integrator voltage signals, VCM and VCR

are subtracted from each other and VREF is added. The resulting maximum voltage at the low pass stage’s

input is given by:

(

)

REF

M

CM

R

CR

OSC

REF

REF

CM

CR

in

LP

V

C

R

C

R

f

V

V

V

V

V

+













⋅

−

⋅

⋅

=

+

−

=

1

1

2

max

,

(5)

This voltage is integrated and averaged by the low pass filter block, which consists of two passive first order

low pass RC-networks decoupled by an operational amplifier. The filter resistors R01 = R02 = 20 kΩ are im-

plemented in CAV424 and the filter capacitors CF1 and CF2, which are external components, define the cor-

ner frequency fC:

Filter

C

C

k

f

⋅

Ω

⋅

=

20

2

1

π

with

CFilter = CF1 or CF2.

(6)

Typically the filter capacitors are chosen in such a way that CF1 = CF2 and fC = 10·fOSC, leading to a ripple

smaller than 1 ‰ of the output signal. The DC voltage at low pass filter’s output is given by:

(

)

REF

M

CM

R

CR

OSC

OSC

OSC

REF

CM

CR

DC

LP

V

C

R

C

R

V

C

R

V

V

V

V

+













⋅

−

⋅

⋅

∆

⋅

⋅

⋅

=

+

−

⋅

=

1

1

8

3

8

3

(7)

Using the circuit in Figure 2 this DC voltage is impedance transformed by the output stage. For this case the

output voltage VOUT at pin 5 is given by equation (8).

The DC voltage can be amplified and offset adjusted using the circuit in Figure 6. For that case the output

voltage VOUT at pin 5 is given by equation (11).

Figure 4: Measurement and reference integrator voltage signals over time