AD73411 datasheet(13/36 Pages) AD

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AD73411

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SPORT2 Overview

SPORT2 is a flexible, full-duplex, synchronous serial port

whose protocol has been designed to allow extra AFE devices

(AD733xx series), up to a maximum of eight I/O channels, to be

connected in cascade to a DSP SPORT (0 or 1). It has a very

flexible architecture that can be configured by programming two

of the internal control registers. SPORT2 has three distinct

modes of operation: Control Mode, Data Mode and Mixed

Control/Data Mode.

In Control Mode (CRA:0 = 0), the device’s internal conﬁgura-

tion can be programmed by writing to the ﬁve internal control

registers. In this mode, control information can be written to or

read from the codec. In Data Mode (CRA:0 = 1), information

that is sent to the device is used to update the decoder section

(DAC), while the encoder section (ADC) data is read from the

device. In this mode, only DAC and ADC data is written to or

read from the device. Mixed mode (CRA:0 = 1 and CRA:1 = 1)

allows the user to choose whether the information being sent to

the device contains either control information or DAC data.

This is achieved by using the MSB of the 16-bit frame as a flag

bit. Mixed mode reduces the resolution to 15 bits, with the MSB

being used to indicate whether the information in the 16-bit frame

is control information or DAC/ADC data.

The SPORT features a single 16-bit serial register that is used for

both input and output data transfers. As the input and output

data must share the same register some precautions must be

observed. The primary precaution is that no information be

written to the SPORT without reference to an output sample

event, which is when the serial register will be overwritten with

the latest ADC sample word. Once the SPORT starts to output

the latest ADC word, it is safe for the DSP to write new control

or data words to the codec. In certain conﬁgurations, data can be

written to the device to coincide with the output sample being

shifted out of the serial register—see section on interfacing devices.

The serial clock rate (CRB:2–3) deﬁnes how many 16-bit words

can be written to a device before the next output sample event

will happen.

The SPORT block diagram, shown in Figure 6, details the six

control registers (A–F), external MCLK to internal DMCLK

divider, and serial clock divider. The divider rates are controlled

by the setting of Control Register B. The AD73411 features a

master clock divider that allows users the flexibility of dividing

externally available high-frequency DSP or CPU clocks to gen-

erate a lower frequency master clock internally in the codec which

may be more suitable for either serial transfer or sampling rate

requirements. The master clock divider has ﬁve divider options

(

÷1 default condition, ÷2, ÷3, ÷4, ÷5) that are set by loading

the master clock divider ﬁeld in Register B with the appropri-

ate code. Once the internal device master clock (DMCLK)

has been set using the master clock divider, the sample rate

and serial clock settings are derived from DMCLK.

The SPORT can work at four different serial clock (SCLK) rates:

chosen from DMCLK, DMCLK/2, DMCLK/4, or DMCLK/8,

where DMCLK is the internal or device master clock resulting

from the external or pin master clock being divided by the

master clock divider. When working at the lower SCLK rate of

DMCLK/8, which is intended for interfacing with slower DSPs,

the SPORT will support a maximum of two devices in cascade

with the sample rate of DMCLK/256.

SPORT2 Register Maps

There are two register banks for the AD73411: the control

bank consists of six read/write registers, each eight bits wide.

Table VII shows the control register map for the AD73411. The

ﬁrst two control registers, CRA and CRB, are reserved for con-

trolling the SPORT. They hold settings for parameters such as

bit rate, internal master clock rate, and device count (used when

more than one AFE is connected in cascade from a single

SPORT). The other three registers; CRC, CRD, and CRE are

used to hold control settings for the ADC, DAC, Reference,

and Power Control sections of the device. Control registers

are written to on the negative edge of SCLK. The data register

bank consists of two 16-bit registers that are the DAC and

ADC registers.

Master Clock Divider

The AD73411 features a programmable master clock divider

that allows the user to reduce an externally available master

clock, at pin MCLK, by one of the ratios 1, 2, 3, 4, or 5, to

produce an internal master clock signal (DMCLK) that is used

to calculate the sampling and serial clock rates. The master

clock divider is programmable by setting CRB:4–6. Table III

shows the division ratio corresponding to the various bit settings.

The default divider ratio is divide-by-one.

Table III. DMCLK (Internal) Rate Divider Settings

MCD2

MCD1

MCD0

DMCLK Rate

MCLK

MCLK/2

MCLK/3

MCLK/4

MCLK/5

MCLK

Serial Clock Rate Divider

The AD73411 features a programmable serial clock divider that

allows users to match the serial clock (SCLK) rate of the data to

that of the DSP engine or host processor. The maximum SCLK

rate available is DMCLK and the other available rates are:

DMCLK/2, DMCLK/4, and DMCLK/8. The slowest rate

(DMCLK/8) is the default SCLK rate. The serial clock divider

is programmable by setting bits CRB:2–3. Table IV shows the

serial clock rate corresponding to the various bit settings.

Table IV. SCLK Rate Divider Settings

SCD1

SCD0

SCLK Rate

DMCLK/8

DMCLK/4

DMCLK/2

DMCLK

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