AD9510-VCOSLASHPCB datasheet(34/60 Pages) AD

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AD9510

Rev. A | Page 34 of 60

Setting the Divide Ratio

The divide ratio is determined by the values written via the SCP

to the registers that control each individual output, OUT0 to

OUT7. These are the even numbered registers beginning at 48h

and going through 56h. Each of these registers is divided into

bits that control the number of clock cycles that the divider

output stays high (high_cycles <3:0>) and the number of clock

cycles that the divider output stays low (low_cycles <7:4>). Each

value is 4 bits and has the range of 0 to 15.

The divide ratio is set by

Divide Ratio = (high_cycles + 1) + (low_cycles + 1)

Example 1:

Set the Divide Ratio = 2

high_cycles = 0

low_cycles = 0

Divide Ratio = (0 + 1) + (0 + 1) = 2

Example 2:

Set Divide Ratio = 8

high_cycles = 3

low_cycles = 3

Divide Ratio = (3 + 1) + (3 + 1) = 8

Note that a Divide Ratio of 8 may also be obtained by setting:

high_cycles = 2

low_cycles = 4

Divide Ratio = (2 + 1) + (4 + 1) = 8

Although the second set of settings produces the same divide

ratio, the resulting duty cycle is not the same.

Setting the Duty Cycle

The duty cycle and the divide ratio are related. Different

divide ratios have different duty cycle options. For example, if

Divide Ratio = 2, the only duty cycle possible is 50%. If the

Divide Ratio = 4, the duty cycle may be 25%, 50%, or 75%.

The duty cycle is set by

Duty Cycle = (high_cycles + 1)/((high_cycles + 1) + (low_cycles + 1))

See Table 17 for the values for the available duty cycles for each

divide ratio.

Table 17. Duty Cycle and Divide Ratio

48h to 56h

Divide Ratio

Duty Cycle (%)

LO <7:4>

HI<3:0>

48h to 56h

Divide Ratio

Duty Cycle (%)

LO <7:4>

HI<3:0>

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