AD9481 datasheet(13/28 Pages) AD

13 / 28 page

AD9481

Rev. 0 | Page 13 of 28

300

SFDR

SNR

SINAD

250

200

150

100

SAMPLE CLOCK (MHz)

Figure 10. SNR, SINAD, SFDR vs. Sample Clock Frequency,

AIN = 70 MHz @ −1 dB

–70

–10

–20

–30

–40

–50

–60

ANALOG INPUT DRIVE LEVEL (dBFS)

SFDR (dBFS)

SFDR (dBc)

60dB

REFERENCE LINE

Figure 11. SFDR vs. AIN Input Level; AIN = 70 MHz @ 250 MSPS

–90

–80

–70

–60

–50

–40

–30

–20

–10

040

100

120

(MHz)

F1, F2 = –7dBFS

2F2–F1 = –65.9dBc

2F1–F2 = –64.9dBc

Figure 12. Two-Tone Intermodulation Distortion

(69.3 MHz and 70.3 MHz; fS = 250 MSPS)

140

IAVDD

IDRVDD

120

100

200

150

250

300

SAMPLE CLOCK (MSPS)

Figure 13. IAVDD and IDRVDD vs. Clock Rate, CLOAD = 5 pF

AIN = 70 MHz @ −1 dBFS

CLOCK POSITIVE DUTY CYCLE (%)

DCS ON

DCS OFF

Figure 14. SNR, SINAD vs. Clock Pulse-Width High,

AIN = 70 MHz @ −1 dBFS, 250 MSPS, DCS On/Off

40.0

50.0

47.5

45.0

42.5

0.5

1.1

0.9

1.5

0.7

1.3

1.7

1.9

EXTERNAL VREF VOLTAGE (V)

SNR

SINAD

SFDR

Figure 15. SNR, SINAD, and SFDR vs. VREF in External Reference Mode, AIN =

70 MHz @ −1 dBFS, 250 MSPS

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