AD9387NK

Preliminary Technical Data

Rev. PrA | Page 6 of 12

Pin No.

BGA

LFCSP

Mnemonic

Description

K7, K8

27, 28

Tx1−/Tx1+

O

Differential Output Channel 1. Differential output of the green data at 10× the

pixel clock rate; TMDS logic level.

K4, K5

24, 25

Tx0−/Tx0+

O

Differential Output Channel 0. Differential output of the blue data at 10× the

pixel clock rate; TMDS logic level.

H10

32

INT

O

Interrupt. Open drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply is

recommended.

J2, J5, J8, K9

19, 23, 29

AVDD

P

1.8 V Power Supply for TMDS Outputs.

D5, D6, D7, E7

1,48,49

DVDD

P

1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to

the digital logic and I/Os. They should be filtered and as quiet as possible.

G4, G5, J1

15, 16, 17

PVDD

P

1.8 V PLL Power Supply. The most sensitive portion of the AD9387NK is the clock

generation circuitry. These pins provide power to the clock PLL. The designer

should provide quiet, noise-free power to these pins.

D4, E4, F4, J4,

G6, J6, K6, F7,

G7, H9, J9

64, Paddle

on bottom

side

GND

P

Ground. The ground return for all circuitry on-chip. It is recommended that the

AD9387NK be assembled on a single, solid ground plane with careful attention

given to ground current paths.

F9

36

SDA

C2

Serial Port Data I/O. This pin serves as the serial port data I/O slave for register

access. Supports CMOS logic levels from 1.8V to 3.3V.

F10

35

SCL

C2

Serial Port Data Clock. This pin serves as the serial port data clock slave for

register access. Supports CMOS logic levels from 1.8V to 3.3V.

E10

37

MDA

C2

Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels

from 1.8 V to 3.3 V.

E9

38

MCL

C2

Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic levels

from 1.8 V to 3.3 V.

G9

34

DDCSDA

C2

Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus.

Supports 5 V CMOS logic level.

G10

33

DDCSCL

C2

Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC

bus. Supports 5 V CMOS logic level.