SSTUB32866_2

© NXP B.V. 2006. All rights reserved.

Product data sheet

Rev. 02 — 9 October 2006

21 of 29

NXP Semiconductors

SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

11.4 Partial parity out load circuit and voltage measurement information

All input pulses are supplied by generators having the following characteristics:

PRR

≤ 10 MHz; Z

Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to

clock inputs

0 V

timing

inputs

output

waveform 2

0.15 V

002aaa503

Fig 24. Partial parity out load circuit

Fig 25. Partial parity out voltage waveforms; propagation delay times with respect to clock

inputs

OUT

DUT

test point

002aaa654

output

002aaa375

CK

CK