Nexperia

74LVC1G79

Single D-type flip-flop; positive-edge trigger

11.1. Waveforms and test circuit

mna443

CP input

Q output

tPHL

tPLH

VM

VM

VOH

VI

GND

D input

VI

GND

VOL

VM

VM

Measurement points are given in Table 9.

VOL and VOH are typical output voltage levels that occur with the output.

Fig. 8. Clock (CP) to output (Q) propagation delay times

mna647

th

tsu

th

tPHL

tW

tPLH

tsu

1/fmax

VM

VM

VM

VI

GND

VI

GND

CP input

D input

VOH

VOL

Q output

Measurement points are given in Table 9.

VOL and VOH are typical output voltage levels that occur with the output.

Fig. 9. Clock (CP) to output (Q) propagation delay times, clock pulse width, D to CP set-up times, the CP to D

hold times and maximum clock pulse frequency

Table 9. Measurement points

Supply voltage

Input

Output

VCC

VM

VM

1.65 V to 1.95 V

0.5 × VCC

0.5 × VCC

2.3 V to 2.7 V

0.5 × VCC

0.5 × VCC

2.7 V

1.5 V

1.5 V

3.0 V to 3.6 V

1.5 V

1.5 V

4.5 V to 5.5 V

0.5 × VCC

0.5 × VCC

74LVC1G79

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Product data sheet

Rev. 14 — 29 March 2022

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