EVAL-AD1938EB datasheet(12/30 Pages) AD

12 / 30 page

AD1935/AD1936/AD1937/AD1938/AD1939

Preliminary Technical Data

Rev. Pr

I | Page 12 of 30

Serial Data Ports—Data Format

The eight DAC channels output or accept a common serial bit clock

and left-right framing clock to clock in the serial data. The four

ADC channels output or accept a common serial bit clock and left-

right framing clock to clock out the data. The clock signals are all

synchronous with the sample rate. In the AUX Modes, set in ADC

Control 1 and DAC Control 0, the DACs use the ADC serial bit

clock and left-right clock as the DAC clock pins are used for the

auxiliary ADC/DAC serial clocks.

The ADC and DAC serial data modes default to I2S. The ports can

also be programmed for left-justified, right-justified and TDM

modes. The word width is 24 bits by default and can be

programmed for 16 or 20 bits. The normal TDM mode can be

daisy-chained with a second AD193X and will support 16 channels

at 48 kHz, 8 channels at 96 kHz or 4 channels at 192 kHz. There is

also a dual-line TDM mode to support 8 channels at 192 kHz.

The special auxiliary modes are provided to allow two external

stereo ADCs and/or two external stereo DACs to be interfaced with

the AD193X to provide up to 8 in/12 out operation or 2 AD193Xs

to be chained for up to 16 in/16 out operation. These modes

provide a glueless interface to a single SHARC serial port, allowing

the DSP to access up to 16 channels of analog I/O. In these modes

many pins are redefined, see table 10. See Figure 18 for details of

these modes.

The following figures show the serial mode formats.

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

LEFT JUSTIFIED MODE––16 BITS TO 24 BITS PER CHANNEL

I2S MODE––16 BITS TO 24 BITS PER CHANNEL

RIGHT JUSTIFIED MODE––SELECT NUMBER OF BITS PER CHANNEL

DSP MODE––16 BITS TO 24 BITS PER CHANNEL

NOTES

1. DSP MODE DOES NOT IDENTIFY CHANNEL

2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 × fS

3. BCLK FREQUENCY IS NORMALLY 64

× LRCLK BUT MAY BE OPERATED IN BURST MODE

MSB

LSB

LEFT CHANNEL

MSB

LSB

MSB

RIGHT CHANNEL

LSB

MSB

1/fS

Figure 13. Stereo Serial Modes

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