AD5384BBC-5 datasheet(16/36 Pages) AD

16 / 36 page

AD5384

Rev. A | Page 16 of 36

Mnemonic

Function

Power Down (Level Sensitive, Active High). PD is used to place the device in low power mode, where AIDD reduces to

2 µA and DIDD to 20 µA. In power-down mode, all internal analog circuitry is placed in low power mode, and the

analog output is configured as a high impedance output or provides a 100 kΩ load to ground, depending on how

the power-down mode is configured. The serial interface remains active during power-down.

No Connect. The user is advised not to connect any signals to these pins.

SPI/ I2C

This pin acts as serial interface mode select. When this input is high SPI mode is selected. When low, I2C is selected.

SCLK/SCL

Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK. This

operates at clock speeds up to 30 MHz.

I2C Mode. In I2C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in I2C

mode is compatible with both 100 kHz and 400 kHz operating modes.

DIN/SDA

Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling

edge of SCLK.

I2C Mode. In I2C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output.

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