Nexperia

74LVC2G86

Dual 2-input EXCLUSIVE-OR gate

6. Pinning information

6.1. Pinning

74LVC2G86

1A

VCC

1B

1Y

2Y

2B

GND

2A

001aab836

1

2

3

4

6

5

8

7

Fig. 4. Pin configuration

SOT505-2 (TSSOP8) and

SOT765-1 (VSSOP8)

74LVC2G86

2B

1Y

VCC

2A

2Y

1B

1A

GND

001aab837

3

6

2

7

1

8

4

5

Transparent top view

Fig. 5. Pin configuration SOT833-1,

SOT1089, SOT1116 and

SOT1203 (XSON8)

8

4

VCC

GND

aaa-027039

Transparent top view

74LVC2G86

1

2

3

1A

1B

2Y

7

6

5

1Y

2B

2A

Fig. 6. Pin configuration SOT1233-2

(X2SON8)

6.2. Pin description

Table 3. Pin description

Symbol

Pin

Description

1A, 2A

1, 5

data input

1B, 2B

2, 6

data input

GND

4

ground (0 V)

1Y, 2Y

7, 3

data output

VCC

8

supply voltage

7. Functional description

Table 4. Function table

H = HIGH voltage level; L = LOW voltage level.

Input

Output

nA

nB

nY

L

L

L

L

H

H

H

L

H

H

H

L

74LVC2G86

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Product data sheet

Rev. 15 — 21 June 2022

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