Nexperia

74LVC04A

Hex inverter

4. Functional diagram

mna342

1A

1Y

1

2

2A

2Y

3

4

3A

3Y

5

6

4A

4Y

9

8

5A

5Y

11

10

6A

6Y

13

12

Fig. 1. Logic symbol

1

1

2

mna343

3

1

4

5

1

6

9

1

8

11

1

10

13

1

12

Fig. 2. IEC logic symbol

mna341

A

Y

Fig. 3. Logic diagram for one gate

5. Pinning information

5.1. Pinning

74LVC04A

1A

VCC

1Y

6A

2A

6Y

2Y

5A

3A

5Y

3Y

4A

GND

4Y

001aac915

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 4. Pin configuration SOT108-1 (SO14) and

SOT402-1 (TSSOP14)

001aac914

74LVC04A

GND(1)

Transparent top view

3Y

4A

3A

5Y

2Y

5A

2A

6Y

1Y

6A

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 5. Pin configuration SOT762-1 (DHVQFN14)

74LVC04A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 11 — 17 September 2021

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