MC68340 datasheet(184/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

5- 47

5.5.2.6 HARDWARE BREAKPOINTS. The CPU32 recognizes hardware breakpoint

requests. Hardware breakpoint requests do not force immediate exception processing, but

are left pending. An instruction breakpoint is not made pending until the instruction

corresponding to the request is executed.

A pending breakpoint can be acknowledged between instructions or at the end of

exception processing. To acknowledge a breakpoint, the CPU performs a read from CPU

space $0 at location $1E (see Section 3 Bus Operation).

If the bus cycle terminates normally, instruction execution continues with the next

instruction, as if no breakpoint request occurred. If the bus cycle is terminated by

BERR,

the CPU begins exception processing. Data returned during this bus cycle is ignored.

Exception processing follows the regular sequence. Vector number 12 (offset $30) is

internally generated. The PC of the currently executing instruction, the PC of the next

instruction to execute, and a copy of the SR are saved on the supervisor stack.

5.5.2.7 FORMAT ERROR. The processor checks certain data values for control

operations. The validity of the stack format code and, in the case of a bus cycle fault

format, the version number of the processor that generated the frame are checked during

execution of the RTE instruction. This check ensures that the program does not make

erroneous assumptions about information in the stack frame.

If the format of the control data is improper, the processor generates a format error

exception. This exception saves a four-word format exception frame and then vectors

through vector table entry number 14. The stacked PC is the address of the RTE

instruction that discovered the format error.

5.5.2.8 ILLEGAL OR UNIMPLEMENTED INSTRUCTIONS. An instruction is illegal if it

contains a word bit pattern that does not correspond to the bit pattern of the first word of a

legal CPU32 instruction, if it is a MOVEC instruction that contains an undefined register

specification field in the first extension word, or if it contains an indexed addressing mode

extension word with bits 5–4 = 00 or bits 3–0

≠ 0000.

If an illegal instruction is fetched during instruction execution, an illegal instruction

exception occurs. This facility allows the operating system to detect program errors or to

emulate instructions in software.

Word patterns with bits 15–12 = 1010 (referred to as A-line opcodes) are unimplemented

instructions. A separate exception vector (vector 10, offset $28) is given to unimplemented

instructions to permit efficient emulation.

Word patterns with bits 15–12 = 1111 (referred to as F-line opcodes) are used for M68000

family instruction set extensions. They can generate an unimplemented instruction

exception caused by the first extension word of the instruction or by the addressing mode

extension word. A separate F-line emulation vector (vector 11, offset $2C) is used for the

exception vector.

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