MC68340 datasheet(174/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

5- 37

5.4.1 State Transitions

The processor is in normal, background, or exception state unless halted.

When the processor fetches instructions and operands or executes instructions, it is in the

normal processing state. The stopped condition, which the processor enters when a

STOP or LPSTOP instruction is executed, is a variation of the normal state in which no

further bus cycles are generated.

Background state is an alternate operational mode used for system debugging. Refer to

5.6 Development Support for more information.

Exception processing refers specifically to the transition from normal processing of a

program to normal processing of system routines, interrupt routines, and other exception

handlers. Exception processing includes the stack operations, the exception vector fetch,

and the filling of the instruction pipeline caused by an exception. Exception processing

ends when execution of an exception handler routine begins. Refer to 5.5 Exception

Processing for comprehensive information.

A catastrophic system failure occurs if the processor detects a bus error or generates an

address error while in the exception processing state. This type of failure halts the

processor. For example, if a bus error occurs during exception processing caused by a

bus error, the CPU32 assumes that the system is not operational and halts.

The halted condition should not be confused with the stopped condition. After the

processor executes a STOP or LPSTOP instruction, execution of instructions can resume

when a trace, interrupt, or reset exception occurs.

5.4.2 Privilege Levels

To protect system resources, the processor can operate with either of two levels of

access—user or supervisor. Supervisor level is more privileged than user level. All

instructions are available at the supervisor level, but execution of some instructions is not

permitted at the user level. There are separate SPs for each level. The S-bit in the SR

indicates privilege level and determines which SP is used for stack operations. The

processor identifies each bus access (supervisor or user mode) via function codes to

enforce supervisor and user access levels.

In a typical system, most programs execute at the user level. User programs can access

only their own code and data areas and are restricted from accessing other information.

The operating system executes at the supervisor privilege level, has access to all

resources, performs the overhead tasks for the user level programs, and coordinates their

activities.

5.4.2.1 SUPERVISOR PRIVILEGE LEVEL. If the S-bit in the SR is set, supervisor

privilege level applies, and all instructions are executable. The bus cycles generated for

instructions executed in supervisor level are normally classified as supervisor references,

and the values of the function codes on FC2–FC0 refer to supervisor address spaces.

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