MC68340 datasheet(102/441 Pages) FREESCALE

102 / 441 page

MOTOROLA

MC68340 USER’S MANUAL

4- 5

SOFTWARE

RESET

REQUEST or

IRQ7

HALT

RESET

BERR

SOFTWARE

WATCHDOG

PERIODIC

INTERRUPT TIMER

IRQ7-IRQ1

CLOCK

RESET

STATUS

PRESCALER

MODULE

CONFIGURATION

REQUEST

BUS

MONITOR

SPURIOUS

INTERRUPT MONITOR

DOUBLE BUS

FAULT MONITOR

Figure 4-2. System Configuration and Protection Function

4.2.2.1 SYSTEM CONFIGURATION. Aspects of the system configuration are controlled

by the MCR and the autovector register (AVR).

The configuration of port B is controlled by the combination of the FIRQ bit in the MCR

and the port B pin assignment register (PPARB). Port B pins can function as dedicated I/O

lines, chip selects, interrupts, or autovector input.

For debug purposes, internal bus accesses can be shown on the external bus. This

function is called show cycles. The SHEN1, SHEN0 bits in the MCR control show cycles.

Bus arbitration can be either enabled or disabled during show cycles.

Arbitration for servicing interrupts is controlled by the value programmed into the interrupt

arbitration (IARB) field of the MCR. Each module that generates interrupts, including the

SIM40, has an IARB field. The value of the IARB field allows arbitration during an IACK

cycle among modules that simultaneously generate the same interrupt level. No two

modules should share the same IARB value. The IARB must contain a value other than $0

for all modules that can generate interrupts; interrupts with IARB = 0 are discarded as

extraneous. The SIM40 arbitrates for both its own interrupts and externally generated

interrupts.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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